This invention relates generally to capacitors and more specifically to capacitors formed in semiconductors, for example, in large scale integrated circuits.
A persistent problem in the design of integrated circuits relates to the economical incorporation of capacitor elements within the integrated circuit structure. It is difficult to provide sufficently large value capacitors on an integrated circuit chip as would avoid the need for discrete capacitors off the chip.
Several kinds of capacitors are used in integrated circuits and essentially, each kind relies on the conventional concept of parallel-plate geometry. The first kind is a junction capacitor formed from the collector and base terminals of an ordinary transistor. The second kind is a thin film capacitor. The latter is constructed along the surface of a semiconductor substrate by first diffusing an n-doped region and then an n+ doped region into a p-type substrate. Next, a thin layer of dielectric material, usually silicon dioxide, is applied, followed by metallic film or layer, usually of aluminum. Examples of these capacitors are disclosed in Schilling, et al., "Electronic Circuits: Discrete and Integrated," pages 331-337 (1968).
Metal-oxide-semiconductor (MOS) capacitors are formed by oxidizing a thin surface layer of a doped semiconductor substrate and applying a metal or other conductive layer to the surface of the oxide. Conventional MOS capacitors are shown in U.S. Pat. No. 3,434,015 to Kilby and in Penney, et al., "MOS Integrated Circuits," pages 53-55 (1972).
Although differing in some respects, the foregoing capacitors have a common characteristic: each employs substrate surface-oriented, parallel conductive plates separated by a dielectric layer whose thickness is normal to the substrate surface. Larger capacitance values are obtained in such capacitors either by increasing the area A of the parallel plates, by decreasing the distance d between the conductive layers, or by increasing the permittivity .epsilon. of the dielectric layer between the conductive layers, in accordance with the formula C=A.epsilon./d.
Several problems arise in applying these techniques. First, the ability to control permittivity .epsilon. is limited to a narrow range of materials compatible with integrated circuit technology. Second, the ability to reduce the distance, d, between the conductors is limited by the thickness of the dielectric layer. If the oxide or other dielectric film is too thin, it is subject to voltage breakdown, resulting in permanent damage to the device. This problem is even greater if the capacitor is p-doped because of the tendency of pinholes to form in oxide layers thermally-grown on p-type semiconductor materials. Consequently, the lower practical limit of oxide-layer thickness in commercial production integrated circuits is about 0.6 .mu.m, although effective oxide layers of lesser thickness have been produced experimentally.
A third problem is that increasing the area, A, of the parallel plates of conventional capacitors consumes valuable surface area of the substrate. This area could otherwise be used for other circuit components. Much of the bulk of the substrate remains unused since circuit components in large scale integrated circuits typically extend less than 1.0 .mu.m below the substrate surface. Simply increasing the depth of surface-oriented capacitors does not increase their capacitance. Hence, conventional techniques of forming integrated circuit capacitors interfere with one of the principal objectives of integrated circuit design--maximizing component packing on a semiconductor chip. Substantial experimentation has been conducted into ion-implantation of semiconductor devices, including the depthwise doping profiles that can be obtained using various implantation techniques. This experimentation is reviewed by D. H. Lee, et al. in "Ion-Implanted Semiconductor Devices," Proc. IEEE, Vol. 62, No. 9, pp. 1241-1255, Sept. 1974, and by V. G. K. Reddi, et al. in "Channeling and dechanneling of ion-implanted phosphorous in silicon," J. Appl. Phys., Vol. 44, No. 7, pp. 2951-2963, July 1973. However, these efforts have been primarily directed to minimizing the depth of ion penetration in constructing transistors rather than maximizing space utilization by capacitors in integrated circuits as disclosed in U.S. Pat. No. 3,653,977 to Gale.
Another problem in making semiconductor capacitors relates to the difficulty of controlling their dimensions and thereby precisely determining their capacitance. The conductive layers are difficult to trim to a desired size and yet consistently obtain smooth, aligned boundaries. Jagged or misaligned boundaries introduce unpredictable fringing effects into the electric field between the conductors. As a result, precision capacitance values can be very difficult to obtain using conventional trimming techniques.
A further problem is voltage-dependency of capacitance values in most types of semiconductor capacitors. Charging such capacitors causes a depletion layer to form in the semiconductor material along the junction or semiconductor oxide layer boundary. The depletion layer acts as a dielectric and increases the effective distance, d, between the conductors, thereby reducing the capacitance of the device. In many integrated circuit designs, this variation can be nearly as great as the gross capacitance of the device. Manipulating biasing in the circuit to control such extreme capacitance variation can impose difficult design constraints on the circuit designer.
Several variations in semiconductor capacitor designs have been tried in an attempt to increase capacitance values. However, these efforts focus primarily on increasing the area of essentially parallel-plate-type conductors. U.S. Pat. No. 3,171,068 to Denkewalter, et al. discloses a semiconductor capacitor comprising concentric hexagonal layers of alternate p-type and n-type material. U.S. Pat. No. 3,460,010 to Domenico, et al. discloses a decoupling capacitor formed on the underside of an integrated circuit chip and employing alternating columns of p-type and n-type material and a metal layer underlying the entire chip. The p-type material is insulated from the metal plate by a thin dielectric film. U.S. Pat. Nos. 3,962,713 and 4,017,885 to Kendall, et al. disclose capacitors formed by selectively etching channels into the semiconductor substrate, forming a thin layer of dielectric over the resultant increased surface area and thereafter forming a metal layer over the dielectric layer. The result is a parallel-plate capacitor having an accordion-like shape.
None of the foregoing patents attempt to increase capacitance by decreasing the distance, d, between oppositely-charged conductors. In the Denkewalter, et al. and Domenico, et al. devices, this distance is determined almost entirely by the dimensions of the depletion layer at the p-n interfaces of the layers. In the Kendall, et al. capacitor, distance d is determined by the thickness of the insulative film separating the conductors. The capacitance values obtained in the foregoing devices are strongly influenced by the voltage-dependent depletion layers in the semiconductors. Also, the Kendall, et al. capacitors are likely to be rather fragile due to the deep etching of the substrate to increase the area of the capacitor.
Accordingly, there remains a need for improved forms of capacitors, and particularly for improved capacitors and capacitor-making techniques applicable to the design and construction of integrated circuits.